1. Field of the Invention
This invention relates to digital data communication, and more specifically to a system and method for providing D.C.-balanced digital code for high-speed, serialized digital data transmission over a transmission line.
2. Description of the Related Art
A transmission line typically has resistance causing both attenuation (loss) and distortion in the signals propagating on the transmission line. In general, the characteristic impedance of a transmission line is frequency-dependent, and can become a dominant portion of the total resistance of the transmission line at high frequencies. At high frequencies, signal attenuation for each frequency component is approximately proportional to the square root of the frequency. Consequently, the length of a transmission line is limited by this attenuation. Thus, for signals in the 10-100 megahertz range, such as video digital data signals, a short transmission line is required between a display and the video controller.
As signal attenuation increases in a transmission line, a small direct current (DC) or low frequency components in the signal may distort the digital signal sufficiently that the attenuated digital signal becomes unintelligible by the receiver, resulting in bit-errors. One method of minimizing DC or low frequency components in the transmission line is to DC-balance the digital signal by coding an equal number of 1""s and 0""s. So long as the number of 1""s and 0""s remain approximately equal, the net voltage on the transmission line is approximately zero.
A DC-balanced coding method can still be susceptible to disparities in single words. Disparity is a measure of the difference in the number of 1""s and 0""s in a bit pattern. Short bursts of 1""s or 0""s in a single word are unavoidable in data transmission. Such single-word xe2x80x981xe2x80x99 and xe2x80x980xe2x80x99 bursts can create a single-word disparity which results in a D.C. bias voltage that exceeds the maximum DC bias tolerable by the receiver, thus causing signal corruption. One coding method which overcomes the single-word disparity problem restricts the maximum run-length of consecutive 1""s or 0""s in a single digital word, thereby preventing a DC voltage build-up on the transmission line.
Various run-length restricted data encoding schemes have been applied. For example, in U.S. Pat. No. 4,530,088 to Hamstra et al., a 4-bit input code is mapped to a 5-bit non-return to zero inverted (NRZI) transmission code, using either a look-up table in ROM or a hardwired logic array to map the 4-bit input word into the 5-bit NRZI code. Hamstra discloses a set of 24 valid characters out of a possible 32 characters. U.S. Pat. No. 4,486,739 to Franaszek et al. also describes a DC-balanced code, and a circuit for translating an 8-bit input word into a 10-bit output word. Like Hamstra, Franaszek uses a ROM or a logic array to map input data to a coded transmission word. In this case, 256 8-bit combinations are mapped into 10-bit values as code and control words.
Similarly, U.S. Pat. No. 5,625,644 to Myers selects 16 code words and 3 control words from a possible 256 words, using a ROM or a logic array to map 4-bit input words into 8-bit output words.
In each of the above methods, the encoder requires substantial valuable die area for the ROM or logic array circuits which map the input codes to the output codes. Further, since a longer word necessarily requires more bandwidth, mapping an input word to a longer output word results in the loss of bandwidth utilization efficiency. For example, in the Myers ""644 patent mentioned above, mapping a 4-bit input word into an 8-bit output word results in a 50% drop in transmission efficiency.
Accordingly, a DC-balanced data encoding system with a high bandwidth utilization efficiency is desired. Preferably, such a DC-balanced code system should not require a ROM or a logic array circuit, so as to reduce the requirements for semiconductor surface area.
The present invention provides a DC-balanced coding system and a method for transmitting high-frequency serial digital data on a transmission line. In one embodiment, a system of the present invention provides an output word that is longer than the input word by one bit, without using a ROM, or a logic gate array, thus minimizing circuit area requirement.
An encoder of the present invention frames or divides an input word into multiple xe2x80x9cframedxe2x80x9d words each shorter or equal to the input word. For example, the present invention may divide or frame a 24-bit input word into 3 channels of 8-bit framed words, or into 4 channels of 6-bit framed words. The framed word may be any number of bits, but limited by both the DC voltage bias resulting from an accumulated imbalance of xe2x80x981xe2x80x99s and xe2x80x980xe2x80x99s transmitted tolerated by the receiver and the bandwidth efficiencies desired. Although greater bandwidth efficiencies can be realized with longer words, the word length is constrained by the maximum allowable single word disparity (SWD) for a word. If all of the bits in an N-bit word were 1s, for example, then the SWD for that word is +N. Similarly, if all of the bits in the word are 0""s, the SWD for that word is xe2x88x92N. If the magnitude of the SWD exceeds the tolerable imbalance, data corruption at the receiver may occur.
The present invention balances the desire for bandwidth efficiency with the need to avoid data corruption. In one embodiment of the present invention, a single inversion bit is appended to an N-bit output word, so that the transmission efficiency is equal to N/(N+1). For a small N, e.g., N equals 2, an efficiency of 67% results. Naturally, a longer word increases the bandwidth efficiency subject to the SWD constraint discussed above. An optimal input word length can be empirically determined in any given system.
In one embodiment, the present invention selects for an output word one of two representations, depending on the input word""s SWD, and a running cumulative word disparity (RWD) of the previous output words. In that embodiment, the output word can be represented either by the input word or the input word""s complement (xe2x80x9cinvertedxe2x80x9d). A counter circuit calculates the SWD of each input word. A running word disparity (RWD) register provides the RWD for the encoder channel. The encoder selects for the output word the one of the two representations that would reduce the magnitude of the RWD, and indicate the selection by the appended inversion bit. The RWD register is updated after transmission of each output word.
In one implementation, a comparator compares the input data word""s SWD to the RWD of the RWD register. The input data word is either inverted or left un-inverted depending upon the values of SWD and RWD. For example, the following selection rules can be applied:
According to another aspect of the present invention, each encoder channel transmits both data and control words. In one embodiment, the control words can each be represented by a xe2x80x9cpositive codexe2x80x9d, with a positive SWD, or a xe2x80x9cnegative codexe2x80x9d, with a negative SWD. For example, the high logic state of a control signal may be indicated by the negative code xe2x80x981110000xe2x80x99 and the positive code xe2x80x981111000xe2x80x99, and the low logic state of the control signal may be represented by the negative code xe2x80x981100000xe2x80x99 and the positive code xe2x80x981111100xe2x80x99. The one of the two representations which reduces the magnitude of the RWD is selected, so that the data on the transmission line remains D.C.-balanced on the average. For example, the following selection rules can be used:
In one embodiment, multiple encoders transmit output words of multiple channels over a single transmission line. In that embodiment, a multiplexor multiplexes the data in each channel onto the single transmission line, and the encoder channels cooperate to ensure that the RWD of the transmitted data is no greater than the maximum imbalance tolerable by the receiver. In another embodiment, each encoder channel transmits on a separate transmission line. Advantageously, as compared to a single transmission line, multiple transmission lines permit lower bit rate in each line to achieve the same total throughput. A lower bit rate results in lower signal attenuation and distortion, and permits longer words as greater imbalance can be tolerated.
In one encoder of the present invention, in addition to a data transmission line, a separate clock transmission line transmits a control signal (e.g., a data enable signal) which indicates to the receiver whether data words or control words are being transmitted over the data transmission line. In that embodiment, the control signal is encoded in the clock timing signal.
Since a control word""s positive and negative codes need not be complementary, an inversion bit on the clock/control signal is not necessary. For example, a 3-high, 4-low bit pattern may be used as negative code for one state of a control signal indicating a data enable mode. A corresponding positive code can be a 3-low, 4-high bit pattern. Similarly, a 2-high, 5-low bit pattern can be used as a negative code for the complementary state of the same control signal. A corresponding positive code for that complementary state can be 2-low, 5-high bit pattern.
In one embodiment, each control word has an equal number of 0""s and 1""s (zero SWD). For example, the data enable high control state may be the bit pattern xe2x80x98000111xe2x80x99 and the data enable low control state may be the bit pattern xe2x80x98111000xe2x80x99.
According to another aspect of this invention, a receiver circuit is provided to receive the encoded output words and the clock control signal. To reconstruct the input word, an inversion bit detector examines the inversion bit.